Semiconductor devices, commonly called integrated circuits, are fabricated on wafers, thin discs typically sliced from a single-crystal silicon ingot. Integrated circuits, comprised of numerous circuit elements, are typically constructed in layers on the wafer surface. The creation of circuit elements and their interconnections involves a complex series of fabrication steps including oxidation, photoresist coating, patterning, etching, ion implantation, resist stripping, and various cleaning, plating and deposition processes. Many of the fabrication processes are repeated numerous times, constructing layer after layer until fabrication is complete. Metal layers (which typically increase in number as device complexity increases) include patterns of conductive material that arc isolated from one another vertically by alternating layers of isolating material. Vertical conductive tunnels called “vias” pass through isolating layers to form conductive pathways between vertically spaced conductive patterns.
Advancing technology requires that transistors switch signals faster, operate at lower power and demonstrate less vulnerability to background cosmic ray particles that could impede operation. Building faster integrated circuits requires smaller internal circuit elements, which tend to produce a lot of heat from the high power typically required. Adequate heat dissipation has proven to be an obstacle to advancing technology. Other electrical problems, must also be addressed, such as “latch-up,” a failure mechanism of CMOS integrated circuits characterized by excessive current drain coupled with functional failure, parametric failure and/or device destruction.
To address these and other issues, the thin silicon-on-insulator (SOI) technique, an alternative concept for fabricating integrated circuits, was developed. Referring now to FIG. 1, instead of using conventional bulk silicon wafers 100 that are essentially a single layer of silicon 110, SOI wafer fabrication utilizes wafers 200, as shown in FIG. 2. SOI wafers 200 include three fundamental layers: a thin surface layer 210 on which transistors are formed, an underlying layer 220 of electrically insulating material, and a thicker supporting silicon wafer 230 underneath. The insulating layer 220, usually made of silicon dioxide and referred to as the “buried oxide” or “BOX,” is usually a few thousand Angstroms thick. The SOI layer 210 is typically between a few hundred Angstroms to several microns thick.
The SOI technique offers the ability to produce transistors that operate at lower parasitic current than those designed on conventional bulk-silicon wafers. This lower parasitic current often results in less battery power drain and die heating. Further, a 20 to 50 percent increase in switching speed may be obtained over similar circuits built on conventional bulk silicon wafers. When transistors are fabricated on an SOI layer, they may switch signals faster, run with a lower current, and tend to be much less vulnerable to signal noise from cosmic ray particles than those built on bulk silicon wafers. Since each transistor on an SOI wafer may be isolated from adjacent transistors by a buried oxide and a shallow trench isolation (STI) region—a non-conductive area of deposited oxide—they are well isolated and virtually immune to latch-up. Consequently, they do not require as much separation from one another and may be spaced closer together than transistors fabricated on conventional bulk silicon wafers. Consequently, SOI technology contributes to more compact die designs, which increases the potential for performance improvements and a higher number of dies per wafer.
Historically, semiconductor fabrication has involved constructing the integrated circuits on the surface of a bulk silicon wafer. Referring now to FIG. 3, a typical structure of a transistor 140 on a bulk silicon wafer 100 is shown. In a conventional process, a layer of silicon dioxide (SiO2) 148 is grown on the surface of the silicon wafer 100. A gate 150 (typically polysilicon) is formed over the silicon dioxide 148. A series of processes then etches a pattern into the silicon dioxide 148, exposing areas of the silicon substrate below. These exposed areas are then “doped,” or implanted with impurities, to give the silicon desired electrical conducting properties. This doping process produces the source 142 and drain 144 regions, conductive impurity regions separated by a channel 146.
When a minimum threshold voltage (Vt) is applied to the gate 150, current will flow through the channel 146, turning the transistor 140 on. A well region 151 may be located underneath the channel 146, extending to the underlying silicon layer 110, and electrically isolating the source 142 and drain 144 from the underlying silicon. Transistors 140 may be electrically isolated from adjacent transistors by STI regions 156. With transistors fabricated on conventional bulk silicon wafers, the channel must fully charge the gate capacitance in order to close and has to discharge the capacitance in order to open again. Thus, transistors constructed on conventional bulk wafers are inherently slower in operation than those constructed on SOI wafers.
Referring now to FIG. 4, a typical construction of a transistor 240 on an SOI wafer 200 is shown. In the SOI process, a transistor 240 is formed on the SOI layer 210, using basically the same fabrication process that was described with FIG. 3. A layer of silicon dioxide (SiO2) 248 is grown on the SOI layer 210. A typically polysilicon gate 250 is formed on top of this silicon dioxide layer 248. A series of processes then etches a pattern into the silicon dioxide 248, exposing areas of the SOI substrate 210 below. The remaining silicon dioxide 248 isolating the gate 250 from the SOI layer 210 is referred to as a “gate oxide.” The exposed SOI areas are then “doped,” to form the source 242 and drain 244, which are separated by a channel 246. Unlike conventional transistor construction on a bulk silicon wafer, in the SOI wafer 200, the source 242, drain 244 and channel 246 are isolated from the bulk silicon layer 230 by a buried oxide layer 220. The transistor 240 may include a well region (not shown) underneath the channel 246.
The greater electrical isolation afforded by the SOI configuration beneath each transistor may reduce the amount of electrical isolation required laterally. As previously mentioned, this additional isolation allows transistors to be spaced closer together. Consequently, when transistors are built within a thin SOI layer, they may be able to switch signals faster and operate at a lower power. Fabricating circuits on SOI wafers allows for more compact integrated circuit designs, allowing smaller IC devices and more dies per wafer, increasing fab productivity. Isolating the active transistor from the rest of the silicon substrate with the buried oxide layer reduces the electrical current leakage that otherwise degrades the performance of the transistor. Since the area of electrically active silicon is limited to the immediate region around the transistor, switching speeds are increased and sensitivity to “soft errors,” a major concern for large-scale data storage and high-volume servers, is greatly reduced.
Fully depleted SOI (FD-SOI) technology is trending continually toward thinner SOI layers under the gate region. As gate lengths shrink, so too must the thickness (TSOI) of the SOI film under the gate region. Referring again to FIG. 4, a thin gate oxide layer 248 isolates the gate 250 from the SOI layer 210. It has been established that a ratio (Lg/TSOI) of gate length 252 to SOI thickness 254 of about 5 for planar FD-SOI devices—as measured under the gate region—provides transistors with optimum operational characteristics. With current FD-SOI device technology, as SOI thickness under the gate is typically less than 10 nanometers (nm), microscopic thickness variations of the SOI film under the gate may complicate the effort to maintain the desired SOI layer thickness.
Processing of fully depleted SOI (FD-SOI) devices generally requires that the thickness of the SOI layer below the gate be in the order of 5-10 nanometers (nm) for devices with gate lengths of 50 nm and below. As gate lengths shrink in the future, the SOI layer for FD-SOI devices may also be required to shrink in thickness, accordingly. Other technologies, such as partially depleted SOI wafers (PD-SOI) generally have much thicker SOI layers, so typically small variations in SOI film uniformity may or may not pose a problem on PD-SOI devices. However, it will be understood that the preferred embodiments will also address SOI film thickness uniformity on a variety of SOI technologies, if warranted.
It is very difficult to attain SOI thickness uniformity across a wafer when dealing with such small dimensions. However, variations in the SOI film thickness may directly translate to significantly increased dispersion—or wider variation—of electrical values across the wafer, including poorer electrical and thermal performance and decreased device yield. A method for improving the SOI film thickness on both the “macro” and “micro” levels of a wafer is desired. Macro-level thickness uniformity refers to achieving SOI film uniformity across the wafer, from die to die. Micro-level thickness uniformity refers to achieving SOI film uniformity on the smaller “gate level,” or from transistor to transistor.
On such small dimensions, variations in SOI thickness may have adverse effects on subsequent fabrication operations, and consequently, on transistor operation. The operational characteristics of a transistor are very dependent on its geometry. Since more than one transistor may work in conjunction, as with a CMOS device, geometric inconsistencies between interconnected transistors may result in variable circuit performance—including heat buildup, voltage irregularities and other electrical problems. As mentioned previously, numerous electrical problems may arise from an SOI layer with a non-uniform under-gate thickness.
As technology advances and gate lengths continue to get smaller, the need to achieve SOI film uniformity will increase. As previously mentioned, since smaller gates will require thinner SOI layers, ever-smaller variations in the SOI thickness will become undesirable and more troublesome. Consequently, a new method is desired to improve thickness uniformity of the SOI layer under the gate region. These and related desires are addressed by the present invention.